03-10-2022, 07:23 PM
The Fundamentals of Digital Electronics, Part 3 - an Oscillator
In part 1 we considered a simple flip/flop, which has two stable states, set and reset. (For that reason a flip/flop is also called a bistable.) In part 2 we looked at edge-triggered flip/flops. Those need a clock to run them. That will be our subject here.
A monostable is a variation on a bistable with one stable state and one transitory state. Monostables are also called one-shots. You trigger a one-shot and it changes state for some period of time, then reverts to the initial, stable state. An oscillator is a further extension. It continually switches states because neither state is stable. A digital oscillator can also be called an astable, or a multivibrator.
First, a bit of background. Once you begin building up more complex functions out of simple AND, OR and NOT functions you find that the tiny delays (called propagation delays) intrinsic to the logic functions begin to add up when you string a number of functions in series. A logic system with lots of independent logic functions (or logic gates) is called asynchronous, or unclocked. It is the designer's burden to make sure that no transitory indeterminate states can exist which might result in logical errors. Once a system gets complex enough, that task becomes over-burdensome. The solution is a clocked, or synchronous system, where state changes all happen at the same time. That way, any propagation delays can ripple through the logic before the next decision point. Modern computers are synchronous devices.
The point of the digression above is that a digital clock signal becomes an important building block before you can go too far with digital circuitry. A digital clock signal is an alternating series of ones and zeros at a particular rate or frequency. We can transform our bistable into an astable by adding two capacitors. Here is the original bistable from part one:
The concept is that a change of state should trigger the next change of state, but only after a short delay. The result is set, pause, reset, pause, set, pause, etc. No external inputs are required, so, we can remove the set and reset inputs. To establish the delay periods, we add two capacitors. The modified circuit now looks like this:
The bases of the two transistors are labeled BQ1 and BQ2. When Q1 turns on, Q2 is forced off by capacitor C1, which couples the negative edge at Q bar to the base of Q2, insuring that Q2 stays off until resistor R4 can turn it on again. Once the current in R4 has drawn the voltage at BQ2 up, Q2 turns on, forcing Q1 off by a the same mechanism in mirror image. If you find that hard to follow, think of the same circuit without the capacitors. You then would have a flip/flop with simultaneous set and reset, causing both transistors to be on. Adding in the capacitors simply forces the other transistor off for a short time after one transistor turns on. That drives the alternation. Here are the waveforms:
Q and Q bar are seen to toggle together, one always high while the other is low. The base of Q1, BQ1, shown in red, drops suddenly when Q2 turns on, then, voltage BQ1 climbs as capacitor C1 is charged by resistor R3. Once transistor Q1 turns on, at about 0.6 volts, the circuit toggles. The process is then repeated at BQ2. Note that the bases go quite a bit below zero volts here. If that is of concern, diodes can easily be attached to the bases to keep them from going more than slightly negative.
You may note that the Q and Q bar signals are not quite symmetrical. That is because they pull down hard when the transistors turn on, but they rise more slowly when they are pulled up by resistors R1 and R2. Smaller value pull-up resistors results in faster operation, but also increases the power supply current required. The tradeoffs between speed and power consumption have gotten a lot of attention over the years, resulting in more sophisticated oscillator circuitry, but the fundamental principles stay the same.
The frequency of operation is set by the RC time constant of R1 and C1 and R4 and C2. Using equal values for both pairs results in a duty cycle near 50%, which is usually desirable. If you wanted a shorter or longer on or off time, ratios can be adjusted accordingly. As a practical matter, the stability of the frequency of oscillation over temperature and the sensitivity of that frequency to changes in power supply voltage are matters of some importance. Those subjects are byond the scope of the discussion here.
The other aspect of a digital oscillator that may complicate the issue is startup. In SPICE simulation, and occasionally on the bench, an oscillator may find an intermediate stable condition in between on and off. That is almost always bad news for a clocking circuit. Typically, it takes a little extra push to get an oscillator started, but once running it will continue indefinitely. That little extra push can be a bit of noise, or any little mismatch between the set and reset action. In SPICE, setting an initial condition is often required to start the circuit. The initial condition statement in the SPICE figure above .ic v(Q) = 5 is what gets it started. Otherwise, ramp the power supply to begin, and insert a slight mismatch in component values. Then the simulated oscillator should start reliably.
That edge-triggered flip/flop from part 2 would be a good place to use the digital clock signal generated here. See part 4, Counters.
Tom Lawson
March 2022
In part 1 we considered a simple flip/flop, which has two stable states, set and reset. (For that reason a flip/flop is also called a bistable.) In part 2 we looked at edge-triggered flip/flops. Those need a clock to run them. That will be our subject here.
A monostable is a variation on a bistable with one stable state and one transitory state. Monostables are also called one-shots. You trigger a one-shot and it changes state for some period of time, then reverts to the initial, stable state. An oscillator is a further extension. It continually switches states because neither state is stable. A digital oscillator can also be called an astable, or a multivibrator.
First, a bit of background. Once you begin building up more complex functions out of simple AND, OR and NOT functions you find that the tiny delays (called propagation delays) intrinsic to the logic functions begin to add up when you string a number of functions in series. A logic system with lots of independent logic functions (or logic gates) is called asynchronous, or unclocked. It is the designer's burden to make sure that no transitory indeterminate states can exist which might result in logical errors. Once a system gets complex enough, that task becomes over-burdensome. The solution is a clocked, or synchronous system, where state changes all happen at the same time. That way, any propagation delays can ripple through the logic before the next decision point. Modern computers are synchronous devices.
The point of the digression above is that a digital clock signal becomes an important building block before you can go too far with digital circuitry. A digital clock signal is an alternating series of ones and zeros at a particular rate or frequency. We can transform our bistable into an astable by adding two capacitors. Here is the original bistable from part one:
The concept is that a change of state should trigger the next change of state, but only after a short delay. The result is set, pause, reset, pause, set, pause, etc. No external inputs are required, so, we can remove the set and reset inputs. To establish the delay periods, we add two capacitors. The modified circuit now looks like this:
The bases of the two transistors are labeled BQ1 and BQ2. When Q1 turns on, Q2 is forced off by capacitor C1, which couples the negative edge at Q bar to the base of Q2, insuring that Q2 stays off until resistor R4 can turn it on again. Once the current in R4 has drawn the voltage at BQ2 up, Q2 turns on, forcing Q1 off by a the same mechanism in mirror image. If you find that hard to follow, think of the same circuit without the capacitors. You then would have a flip/flop with simultaneous set and reset, causing both transistors to be on. Adding in the capacitors simply forces the other transistor off for a short time after one transistor turns on. That drives the alternation. Here are the waveforms:
Q and Q bar are seen to toggle together, one always high while the other is low. The base of Q1, BQ1, shown in red, drops suddenly when Q2 turns on, then, voltage BQ1 climbs as capacitor C1 is charged by resistor R3. Once transistor Q1 turns on, at about 0.6 volts, the circuit toggles. The process is then repeated at BQ2. Note that the bases go quite a bit below zero volts here. If that is of concern, diodes can easily be attached to the bases to keep them from going more than slightly negative.
You may note that the Q and Q bar signals are not quite symmetrical. That is because they pull down hard when the transistors turn on, but they rise more slowly when they are pulled up by resistors R1 and R2. Smaller value pull-up resistors results in faster operation, but also increases the power supply current required. The tradeoffs between speed and power consumption have gotten a lot of attention over the years, resulting in more sophisticated oscillator circuitry, but the fundamental principles stay the same.
The frequency of operation is set by the RC time constant of R1 and C1 and R4 and C2. Using equal values for both pairs results in a duty cycle near 50%, which is usually desirable. If you wanted a shorter or longer on or off time, ratios can be adjusted accordingly. As a practical matter, the stability of the frequency of oscillation over temperature and the sensitivity of that frequency to changes in power supply voltage are matters of some importance. Those subjects are byond the scope of the discussion here.
The other aspect of a digital oscillator that may complicate the issue is startup. In SPICE simulation, and occasionally on the bench, an oscillator may find an intermediate stable condition in between on and off. That is almost always bad news for a clocking circuit. Typically, it takes a little extra push to get an oscillator started, but once running it will continue indefinitely. That little extra push can be a bit of noise, or any little mismatch between the set and reset action. In SPICE, setting an initial condition is often required to start the circuit. The initial condition statement in the SPICE figure above .ic v(Q) = 5 is what gets it started. Otherwise, ramp the power supply to begin, and insert a slight mismatch in component values. Then the simulated oscillator should start reliably.
That edge-triggered flip/flop from part 2 would be a good place to use the digital clock signal generated here. See part 4, Counters.
Tom Lawson
March 2022