03-14-2022, 05:39 PM
The Fundamentals of Digital Electronics, Part 4 - Synchronous and Asynchronous Counters
In part 2 we covered an edge-triggered flip/flop, generally called a type D flip/flop, or a type D latch. We also showed how a type D flip/flop can divide a frequency by two. In part 3, we showed a digital oscillator, or clock generator circuit. Here, we will examine counters for timing functions, and compare synchronous and asynchronous approaches to timing circuits.
A counter is string of latches connected to a timing signal. If your clock runs at 1 Megahertz, and you divide by two with a D-Flop, you have a 500kHz signal. That can be fed to another divide by two stage for 250 kHz, then 125 kHz, etc. The simplest counter is called a ripple counter. A four stage ripple counter will divide by 16. See below:
The waveforms look simple enough, too. Here we start from 1 MHz:
Each succeeding stage cuts the output frequency in half. Digital timing circuits generally use oscillators stabilized by crystals or resonators which are available at specific frequencies. Knowing the input frequency, and being able to count a certain number of pulses, allows accurate and reproducible timing.
The analog timing circuits that digital timers replaced depended on resistors and capacitors to create timing delays. The delay is proportional to the resistance times the capacitance. Component tolerances and temperature effects alter the timing. Also, longer delays require higher component values. Measuring long periods with analog delays is especially difficult. You can't make a resistor value arbitrarily large. At some number of Megohms the leakage currents become dominant. In theory you can make a capacitor arbitrarily large, but it becomes expensive and bulky. Very long analog delays require voltage sensing with excellent long-term stability. The voltage sensor in the timing circuit will be waiting for the end of a long exponential tail. A little bit of offset drift can then cause a large timing error. With the advent of CMOS logic chips, we jumped at the chance to use ripple counters with many stages to count long delays.
A CD4020 is a ripple counter with 14 stages, which allows a 32,768 kHz crystal to be divided down by 2 to the 14th, for an output frequency of 2 Hz. It takes a lot of stages to get down to that half-second period, but it is only one 16 pin chip. The propagation delay in a CD4020B chip running on 5 volts could be as high as 360nS. By the time a clock edge propagated through all 14 stages, 5 microseconds could pass. That can matter more than it might seem.
If you need a timing period that is not one of those available when dividing a standard crystal or resonator frequency by some power of two, you need to add gating for that. In the simple example above, lets say you put an AND gate on the 8us period and the 1 us period, as below:
That should be straightforward, no? Well, actually not. See the waveforms:
The first stage of the counter acts a little bit earlier than the later stage, due to propagation delays. As a result, the first stage output rises before the third stage drops, so you see an unwanted slice at the transition. Unwanted slices are bad news in edge-triggered circuits. The more stages, the more delay, and the heftier the slice becomes. Problems of this sort can be hard to troubleshoot because they create marginal circumstances that can act inconsistently. Also, narrow, rare spikes are hard to see on an oscilloscope. The answer is a different kind of counter, called a synchronous counter.
A synchronous counter uses a common clock to update all the stages at the same clock edge. It adds quite a bit to the internal complexity of the counter to accomplish that. For example, an ordinary 74HC162 type 4-bit synchronous counter has 4 internal type D flip/flops, just like the ripple counter shown above, but it also requires 33 other logic gates of various descriptions to make it all work synchronously. Once the principles are understood, a designer uses the counter chip as a building block, so that extra complexity is hidden.
Various special-purpose digital counters were, and are, offered for particular applications. Those include decade counters with divide-by-ten gating built-in, up/down counters, and Binary Coded Decimal (BCD) counters. BCD counters are intended for use with digital displays where any given digit is a number from 0 to 9. A BCD counter wraps around from 9 back to zero. There are also counters with what are called 7-segment decoded outputs. That means the BCD or hexadecimal digit held in the 4-bit counter appears at the output pins as the state of the seven segments of a displayed character. For hexadecimal, above 9, a digit counts A, B, C, D, E, F, and then back to zero.
Using synchronous counters allows arbitrary gating of periods, but even then, care is still required to avoid very brief slices. Most ordinary synchronous counters come 4 stages to a package. It would take four four-bit chips to exceed those 14 stages available from the CD4020. Higher density digital circuitry came to the rescue. The 8254 timer chip (now obsolete), as used in the original IBM PC, is a 24 pin chip with three synchronous programmable 16 bit timers. With 48 stages of synchronous counting available, digital counting quickly took over most timing applications.
By now we have covered the fundamental building blocks needed for the evolution of digital processing. Simple logic functions can be combined to obtain complex logic functions. Latches store information. Oscillators and counters provide timing, and analog-to-digital circuits bring in data from sensors. Numeric or alphanumeric displays present the results. The first blockbuster digital computing application was the pocket calculator introduced in the early 1970's. The promise of the new digital technology was quickly evident. It took only 6 more years to get to the introduction of the Apple ][ personal computer.
Subsequent discussions might show how an early, simple microprocessor could be built and programmed to perform useful tasks. This isn't ancient history here, it all took off in the 1970's.
Tom Lawson
March 2022
In part 2 we covered an edge-triggered flip/flop, generally called a type D flip/flop, or a type D latch. We also showed how a type D flip/flop can divide a frequency by two. In part 3, we showed a digital oscillator, or clock generator circuit. Here, we will examine counters for timing functions, and compare synchronous and asynchronous approaches to timing circuits.
A counter is string of latches connected to a timing signal. If your clock runs at 1 Megahertz, and you divide by two with a D-Flop, you have a 500kHz signal. That can be fed to another divide by two stage for 250 kHz, then 125 kHz, etc. The simplest counter is called a ripple counter. A four stage ripple counter will divide by 16. See below:
The waveforms look simple enough, too. Here we start from 1 MHz:
Each succeeding stage cuts the output frequency in half. Digital timing circuits generally use oscillators stabilized by crystals or resonators which are available at specific frequencies. Knowing the input frequency, and being able to count a certain number of pulses, allows accurate and reproducible timing.
The analog timing circuits that digital timers replaced depended on resistors and capacitors to create timing delays. The delay is proportional to the resistance times the capacitance. Component tolerances and temperature effects alter the timing. Also, longer delays require higher component values. Measuring long periods with analog delays is especially difficult. You can't make a resistor value arbitrarily large. At some number of Megohms the leakage currents become dominant. In theory you can make a capacitor arbitrarily large, but it becomes expensive and bulky. Very long analog delays require voltage sensing with excellent long-term stability. The voltage sensor in the timing circuit will be waiting for the end of a long exponential tail. A little bit of offset drift can then cause a large timing error. With the advent of CMOS logic chips, we jumped at the chance to use ripple counters with many stages to count long delays.
A CD4020 is a ripple counter with 14 stages, which allows a 32,768 kHz crystal to be divided down by 2 to the 14th, for an output frequency of 2 Hz. It takes a lot of stages to get down to that half-second period, but it is only one 16 pin chip. The propagation delay in a CD4020B chip running on 5 volts could be as high as 360nS. By the time a clock edge propagated through all 14 stages, 5 microseconds could pass. That can matter more than it might seem.
If you need a timing period that is not one of those available when dividing a standard crystal or resonator frequency by some power of two, you need to add gating for that. In the simple example above, lets say you put an AND gate on the 8us period and the 1 us period, as below:
That should be straightforward, no? Well, actually not. See the waveforms:
The first stage of the counter acts a little bit earlier than the later stage, due to propagation delays. As a result, the first stage output rises before the third stage drops, so you see an unwanted slice at the transition. Unwanted slices are bad news in edge-triggered circuits. The more stages, the more delay, and the heftier the slice becomes. Problems of this sort can be hard to troubleshoot because they create marginal circumstances that can act inconsistently. Also, narrow, rare spikes are hard to see on an oscilloscope. The answer is a different kind of counter, called a synchronous counter.
A synchronous counter uses a common clock to update all the stages at the same clock edge. It adds quite a bit to the internal complexity of the counter to accomplish that. For example, an ordinary 74HC162 type 4-bit synchronous counter has 4 internal type D flip/flops, just like the ripple counter shown above, but it also requires 33 other logic gates of various descriptions to make it all work synchronously. Once the principles are understood, a designer uses the counter chip as a building block, so that extra complexity is hidden.
Various special-purpose digital counters were, and are, offered for particular applications. Those include decade counters with divide-by-ten gating built-in, up/down counters, and Binary Coded Decimal (BCD) counters. BCD counters are intended for use with digital displays where any given digit is a number from 0 to 9. A BCD counter wraps around from 9 back to zero. There are also counters with what are called 7-segment decoded outputs. That means the BCD or hexadecimal digit held in the 4-bit counter appears at the output pins as the state of the seven segments of a displayed character. For hexadecimal, above 9, a digit counts A, B, C, D, E, F, and then back to zero.
Using synchronous counters allows arbitrary gating of periods, but even then, care is still required to avoid very brief slices. Most ordinary synchronous counters come 4 stages to a package. It would take four four-bit chips to exceed those 14 stages available from the CD4020. Higher density digital circuitry came to the rescue. The 8254 timer chip (now obsolete), as used in the original IBM PC, is a 24 pin chip with three synchronous programmable 16 bit timers. With 48 stages of synchronous counting available, digital counting quickly took over most timing applications.
By now we have covered the fundamental building blocks needed for the evolution of digital processing. Simple logic functions can be combined to obtain complex logic functions. Latches store information. Oscillators and counters provide timing, and analog-to-digital circuits bring in data from sensors. Numeric or alphanumeric displays present the results. The first blockbuster digital computing application was the pocket calculator introduced in the early 1970's. The promise of the new digital technology was quickly evident. It took only 6 more years to get to the introduction of the Apple ][ personal computer.
Subsequent discussions might show how an early, simple microprocessor could be built and programmed to perform useful tasks. This isn't ancient history here, it all took off in the 1970's.
Tom Lawson
March 2022