03-03-2021, 08:05 PM
First, see my earlier post showing a 4-BIT SAR converter using binarily-weighted resistors.
Here, the A/D converter is extended to 8 Bits, and the SAR uses what is called an R/2R network. As you extend a series of binarily-weighted resistors, the values required get critical by the time you have stretched to 8 bits. If we start at 1K, the series becomes: 2K, 4K, 8K, 16K, 32K, 64K, 128K. The tolerance of the smaller resistors must be 0.2% if you want to have anything close to 256 equal steps. Plus, in the real world, those different value resistors would need to track each other over the operating temperature range.
Another consideration is the loading placed on the logic outputs which must drive the resistors. A 1k load will pull a logic output away from the theoretic zero or one voltage. The minimum resistance for a particular specified accuracy would change with logic family, but if the minimum resistor needed to be 10K, that would push the value of the largest resistor to 1.28 meg ohms. Noise pickup becomes more of a problem as the impedance values go up.
The answer is an R/2R network, as shown here, with R= 5K and 2R= 10K.
The rigorous technical explanation of why an R/2R ladder works involves Thevenization, which is the application of Thevenin's Theorem. A quick, intuitive explanation is a good place to start. Imagine a one-bit system with just the right-hand bit. A latched one puts 0.5v at the junction of the two equal resistors (both 2R), and 0v if the data is zero. To add a second, less significant bit, replace the the 2R resistor to ground with a 1R resistor and another latch and two more 2R resistors. If both bits are ones, the parallel combination of the two right-hand 2R resistors to 1 and to 0 volts respectively is equivalent to a 1R resistor to 0.5V. (That's Thevenization.) Add in the series 1R resistor, and you have a 2R/2R resistive divider picking the middle of 1 and 0.5 volts, or 0.75 volts. As the pattern repeats, each bit added on the right adds half the weight of the adjacent bit to the left.
It is a lot easier to match resistors of equal value for absolute tolerance and for temperature coefficient. Also, the need for extreme, but precise, ratios disappears. Then, remember the loading issues. Having all 2R values in series with the latch outputs matches up the behavior of the various bits. If you use an IC that includes an SAR, it probably contains an R/2R ladder.
Here is the output of the converter digitizing a 50 Hz sine wave. The input frequency is sloweed down to eliminate any noticeable errors due to the change in input voltage during the conversion.
The additional 4 bits are a simple extension of the first 4 bits. The timing ramp, t, now ramps to 9, for 8 bit periods plus one period to capture the answer before the start of the next conversion. The detail of the mid-scale transition is shown below. Note that those 4 additional bits improve the resolution by a factor of 16. Each step is now 1 volt / 256, or a little under 4 mv. If you want to accurately capture the voltage at an instant of time, you would need to put a sample and hold circuit in front of the converter. You could then sample during the 9th timing period and hold during the other 8.
Note that even during the fastest slewing portion of the input sine wave, two or three conversions occur between steps in the answer. The conversion rate is 100 KHz, so each of the 9 periods is 1.111 us. As expected, just above mid-scale the MSB remains set and all the other bits are cleared. Just below mid-scale, the MSB is cleared, and all the other bits are set. That is the binary transition from 1000 0000 to 0111 1111. In SPICE, that transition is just like the others. On the bench, it is always the hardest transition to get just right.
Tom Lawson
March 3, 2021
Here, the A/D converter is extended to 8 Bits, and the SAR uses what is called an R/2R network. As you extend a series of binarily-weighted resistors, the values required get critical by the time you have stretched to 8 bits. If we start at 1K, the series becomes: 2K, 4K, 8K, 16K, 32K, 64K, 128K. The tolerance of the smaller resistors must be 0.2% if you want to have anything close to 256 equal steps. Plus, in the real world, those different value resistors would need to track each other over the operating temperature range.
Another consideration is the loading placed on the logic outputs which must drive the resistors. A 1k load will pull a logic output away from the theoretic zero or one voltage. The minimum resistance for a particular specified accuracy would change with logic family, but if the minimum resistor needed to be 10K, that would push the value of the largest resistor to 1.28 meg ohms. Noise pickup becomes more of a problem as the impedance values go up.
The answer is an R/2R network, as shown here, with R= 5K and 2R= 10K.
The rigorous technical explanation of why an R/2R ladder works involves Thevenization, which is the application of Thevenin's Theorem. A quick, intuitive explanation is a good place to start. Imagine a one-bit system with just the right-hand bit. A latched one puts 0.5v at the junction of the two equal resistors (both 2R), and 0v if the data is zero. To add a second, less significant bit, replace the the 2R resistor to ground with a 1R resistor and another latch and two more 2R resistors. If both bits are ones, the parallel combination of the two right-hand 2R resistors to 1 and to 0 volts respectively is equivalent to a 1R resistor to 0.5V. (That's Thevenization.) Add in the series 1R resistor, and you have a 2R/2R resistive divider picking the middle of 1 and 0.5 volts, or 0.75 volts. As the pattern repeats, each bit added on the right adds half the weight of the adjacent bit to the left.
It is a lot easier to match resistors of equal value for absolute tolerance and for temperature coefficient. Also, the need for extreme, but precise, ratios disappears. Then, remember the loading issues. Having all 2R values in series with the latch outputs matches up the behavior of the various bits. If you use an IC that includes an SAR, it probably contains an R/2R ladder.
Here is the output of the converter digitizing a 50 Hz sine wave. The input frequency is sloweed down to eliminate any noticeable errors due to the change in input voltage during the conversion.
The additional 4 bits are a simple extension of the first 4 bits. The timing ramp, t, now ramps to 9, for 8 bit periods plus one period to capture the answer before the start of the next conversion. The detail of the mid-scale transition is shown below. Note that those 4 additional bits improve the resolution by a factor of 16. Each step is now 1 volt / 256, or a little under 4 mv. If you want to accurately capture the voltage at an instant of time, you would need to put a sample and hold circuit in front of the converter. You could then sample during the 9th timing period and hold during the other 8.
Note that even during the fastest slewing portion of the input sine wave, two or three conversions occur between steps in the answer. The conversion rate is 100 KHz, so each of the 9 periods is 1.111 us. As expected, just above mid-scale the MSB remains set and all the other bits are cleared. Just below mid-scale, the MSB is cleared, and all the other bits are set. That is the binary transition from 1000 0000 to 0111 1111. In SPICE, that transition is just like the others. On the bench, it is always the hardest transition to get just right.
Tom Lawson
March 3, 2021